DSpace
 

Depot Institutionnel de l'UMBB >
Publications Scientifiques >
Communications Internationales >

Veuillez utiliser cette adresse pour citer ce document : http://dlibrary.univ-boumerdes.dz:8080/handle/123456789/3037

Titre: Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming
Auteur(s): Kassem, Abdallah
Wang, J.
Khouas, Abdelhakim
Boukadoum, Mounir
Mots-clés: Pipelined sampled
delay focusing CMOS implementation
ultrasonic digital beamforming
Date de publication: 2003
Editeur: IEEE
Collection/Numéro: System-on-Chip for Real-Time Applications, 2003. Proceedings; pp. 1-4
Résumé: The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of a pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18􀁐m technology and the resulting active layout area is 0.14 mm2, while its total power consumption is below 40 mW
URI/URL: http://dlibrary.univ-boumerdes.dz:8080/handle/123456789/3037
ISSN: 0-7695-1929-6
Collection(s) :Communications Internationales

Fichier(s) constituant ce document :

Fichier Description TailleFormat
Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming.pdf255,99 kBAdobe PDFVoir/Ouvrir
View Statistics

Tous les documents dans DSpace sont protégés par copyright, avec tous droits réservés.

 

Valid XHTML 1.0! Ce site utilise l'application DSpace, Version 1.4.1 - Commentaires