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Titre: | Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation |
Auteur(s): | Chenouf, Amel Djezzar, Boualem Bentarzi, Hamid Benabdelmoumene, Abdelmadjid |
Mots-clés: | Sizing CMOS 6T-SRAM cell NBTI ageing mitigation |
Date de publication: | 2020 |
Editeur: | IEEE |
Collection/Numéro: | IET Circuits, Devices and Systems, 14(4);PP. 555-561 |
Résumé: | This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability |
URI/URL: | https://ieeexplore.ieee.org/document/9139598 http://dlibrary.univ-boumerdes.dz:8080/handle/123456789/5980 |
ISSN: | 19729283 |
Collection(s) : | Publications Internationales
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