Hardware Design and FPGA Implementation for Road Plane Extraction Based on V-disparity Approach

Abstract

Accurate and real-time free space and obstacles detection is a task of great interest to the navigation of mobile robots, and the integration to existing vehicle's safety systems. This paper presents a novel approach for road plane extraction, free space and obstacles discrimination using stereovision. The estimated road profile from V-disparity images allows robust extraction of the road features from pixels classification of the disparity map. The proposed hardware architecture combines parallel processing with dedicated and optimized modules to reduce logic resource utilization, and accelerate processing time. This architecture is implemented on Cyclone IV E FPGA based prototyping board, and tested using real stereoscopic images of different environments. Experimental results demonstrate the efficiency and accuracy of the proposed method. The implemented system can treat up to 490 and 122 frames/s for stereoscopic images of 320×240 and 640×480 pixels respectively